Parallelism Utilization in Embedded Reconfigurable Computing Systems: A Survey of Recent Trends

Recently, embedded reconfigurable computing has attracted great attention due to its potential to accelerate application execution. Its key feature is the ability to perform computations in hardware to increase performance, while retaining much of the flexibility of a software solution. Researchers in this field have reported substantial performance improvements for a variety of different applications like cryptography, multimedia processing, genetics, networking and DSP. Embedded reconfigurable computing systems can lend themselves to high performance computing by taking advantage of parallelism at different levels of granularity, ranging from fine grained instruction level to coarse grained process and/or task level parallelism. It is often necessary to use different parallel processing techniques to fully take advantage of these systems. In this survey, we explore recent enhancements to this new field of computing, considering the embedded reconfigurable hardware architectures and software facilities targeting these systems. The focus of the survey is on the employment of parallelism which seems to be a key feature in application development for embedded reconfigurable systems. More precisely, four different levels of parallelism indicated by Instruction Level, Data/Loop Level, Task Level, and Process/Thread Level, are introduced and distinguished by properties identified for each category. Various reconfigurable systems incorporating one or a combination of these attributes are investigated. Finally, we generally try to identify the major problems that limit the embedded reconfigurable computing systems from reaching their maximum potentials.